Memory devices have numerous applications for storing data. Some memory devices store a specific state by altering characteristics pertaining to the threshold of conduction of the device. Typically, in order to program data into the memory device, the threshold of conduction for the memory device is configured such that the conduction of current represents a first state and the non-conduction of current represents a second state. However, such a memory device is configurable to store a range of threshold levels. Such a device is suitable to store analog data. The storing of analog data permits storage of multiple bits of data in a single memory cell. This is known as a multi-level cell.
There are prior patents that discuss multi-level storage. U.S. Pat. No. 5,043,940 of Harrari for FLASH EEPROM MEMORY SYSTEMS HAVING MULTISTATE STORAGE CELLS ("Harrari") defines multi-level states in terms of the threshold voltage V.sub.t of a split-channel flash electrically erasable read only memory (EEprom) memory cell. Using these four states, Harrari is able to store two bits of data per memory cell by applying multiple programming pulses to each memory cell. U.S. Pat. No. 5,163,021 of Mehrota et al. for MULTI-STATE EEPROM READ AND WRITE CIRCUITS AND TECHNIQUES ("Mehrota") also describes multilevel memory system. Like Harrari, Mehrota defines four states in terms of memory cell threshold voltage.
However, when storing more than a single bit per cell, the reliability of the memory system is diminished. Therefore, it is desirable to increase the reliability of a memory system capable of storing more than a single bit per cell. Because the integrity of data storage is more critical for some types of data than for others, it is desirable to store more than a single bit per cell in portions of a memory while storing a single bit per cell in other portions of the memory.